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| 64-Lane 16-Port PCI Express(R) System Interconnect Switch (R) 89HPES64H16 Data Sheet Device Overview The 89HPES64H16 is a member of the IDT PRECISETM family of PCI Express(R) switching solutions. The PES64H16 is a 64-lane, 16-port system interconnect switch optimized for PCI Express packet switching in high-performance applications, supporting multiple simultaneous peer-to-peer traffic flows. Target applications include servers, storage, communications, and embedded systems. Features High Performance PCI Express Switch - Sixteen maximum switch ports * Eight main ports each of which consists of 8 SerDes * Each x8 main port can further bifurcate to 2 x4-ports - Sixty-four 2.5 Gbps embedded SerDes * Supports pre-emphasis and receive equalization on per-port basis - Delivers 256 Gbps (32 GBps) of aggregate switching capacity - Low-latency cut-through switch architecture - Support for Max Payload Size up to 2048 bytes - Supports two virtual channels and eight traffic classes - PCI Express Base Specification Revision 1.1 compliant Flexible Architecture with Numerous Configuration Options - Port arbitration schemes utilizing round robin algorithms - Virtual channels arbitration based on priority - Automatic per port link width negotiation to x8, x4, x2 or x1 - Automatic lane reversal on all ports - Automatic polarity inversion on all lanes - Supports locked transactions, allowing use with legacy software - Ability to load device configuration from serial EEPROM - Ability to control device via SMBus Highly Integrated Solution - Requires no external components - Incorporates on-chip internal memory for packet buffering and queueing - Integrates sixty-four 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features - Redundant upstream port failover capability - Supports optional PCI Express end-to-end CRC checking Block Diagram x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 SerDes DL/Transaction Layer SerDes DL/Transaction Layer SerDes DL/Transaction Layer SerDes DL/Transaction Layer Route Table Port Arbitration 16-Port Switch Core Frame Buffer Scheduler DL/Transaction Layer DL/Transaction Layer DL/Transaction Layer DL/Transaction Layer SerDes SerDes SerDes SerDes x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 64 PCI Express Lanes Up to 8 x8 ports or 16 x4 Ports Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 49 (c) 2007 Integrated Device Technology, Inc. July 19, 2007 IDT 89HPES64H16 Data Sheet - Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) - Supports optional PCI Express Advanced Error Reporting - Supports PCI Express Hot-Plug * Compatible with Hot-Plug I/O expanders used on PC motherboards - Supports Hot-Swap Power Management - Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) * Supports powerdown modes at the link level (L0, L0s, L1, L2/L3 Ready and L3) and at the device level (D0, D3hot) - Unused SerDes disabled Testability and Debug Features - Built in SerDes Pseudo-Random Bit Stream (PRBS) generator - Ability to read and write any internal register via the SMBus - Ability to bypass link training and force any link into any mode - Provides statistics and performance counters Thirty-two General Purpose Input/Output pins - Each pin may be individually configured as an input or output - Each pin may be individually configured as an interrupt input - Some pins have selectable alternate functions Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with 1mm ball spacing minimum number of board layers. It provides 256 Gbps of aggregated, full-duplex switching capacity through 64 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.1. The PES64H16 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers. The PES64H16 can operate either as a store and forward switch or a cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and two Virtual Channels (VC) with sophisticated resource management to enable efficient switching and I/O connectivity. SMBus Interface The PES64H16 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES64H16, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES64H16 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. Product Description Utilizing standard PCI Express interconnect, the PES64H16 provides the most efficient system interconnect switching for applications requiring high throughput, low latency, and simple board layout with a Non-bifurcated x8 x8 x8 Fully Bifurcated x4 x4 x4 x4 x4 4 5 6 7 32 10 15 x8 14 13 x8 12 4 3 2 1 0 15 x4 14 13 x4 x4 x4 x4 x4 x4 5 6 x8 89 x8 10 11 x8 7 8 x4 9 x4 10 x4 11 x4 12 Figure 2 Port Configuration Examples Note: The configurations in the above diagram show the maximum port widths. The PES64H16 can negotiate to narrower port widths -- x4, x2, or x1. 2 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Bit 1 2 3 4 5 6 7 Slave SMBus Address SSMBADDR[1] SSMBADDR[2] SSMBADDR[3] 0 SSMBADDR[5] 1 1 Master SMBus Address MSMBADDR[1] MSMBADDR[2] MSMBADDR[3] MSMBADDR[4] 1 0 1 Table 1 Master and Slave SMBus Address Assignment As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES64H16 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES64H16 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES64H16 may be configured to operate in a split configuration as shown in Figure 3(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES64H16 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. PES64H16 Processor SMBus Master Serial EEPROM ... Other SMBus Devices PES64H16 Processor SMBus Master ... Other SMBus Devices SSMBCLK SSMBDAT MSMBCLK MSMBDAT SSMBCLK SSMBDAT MSMBCLK MSMBDAT Serial EEPROM (a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses Figure 3 SMBus Interface Configuration Examples Hot-Plug Interface The PES64H16 supports PCI Express Hot-Plug on each downstream port (ports 1 through 15). To reduce the number of pins required on the device, the PES64H16 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES64H16 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES64H16. In response to an I/O expander interrupt, the PES64H16 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES64H16 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. 3 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin Description The following tables lists the functions of the pins provided on the PES64H16. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differential signals end with a suffix "N" or "P." The differential signal ending in "P" is the positive portion of the differential pair and the differential signal ending in "N" is the negative portion of the differential pair. Signal PE0RP[3:0] PE0RN[3:0] PE0TP[3:0] PE0TN[3:0] PE1RP[3:0] PE1RN[3:0] PE1TP[3:0] PE1TN[3:0] PE2RP[3:0] PE2RN[3:0] PE2TP[3:0] PE2TN[3:0] PE3RP[3:0] PE3RN[3:0] PE3TP[3:0] PE3TN[3:0] PE4RP[3:0] PE4RN[3:0] PE4TP[3:0] PE4TN[3:0] PE5RP[3:0] PE5RN[3:0] PE5TP[3:0] PE5TN[3:0] PE6RP[3:0] PE6RN[3:0] PE6TP[3:0] PE6TN[3:0] PE7RP[3:0] PE7RN[3:0] PE7TP[3:0] PE7TN[3:0] Type I O I Name/Description PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port. PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4. PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for port 6. PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7. PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. Table 2 PCI Express Interface Pins (Part 1 of 2) O I O I O I O I O I O I O 4 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal PE8RP[3:0] PE8RN[3:0] PE8TP[3:0] PE8TN[3:0] PE9RP[3:0] PE9RN[3:0] PE9TP[3:0] PE9TN[3:0] PE10RP[3:0] PE10RN[3:0] PE10TP[3:0] PE10TN[3:0] PE11RP[3:0] PE11RN[3:0] PE11TP[3:0] PE11TN[3:0] PE12RP[3:0] PE12RN[3:0] PE12TP[3:0] PE12TN[3:0] PE13RP[3:0] PE13RN[3:0] PE13TP[3:0] PE13TN[3:0] PE14RP[3:0] PE14RN[3:0] PE14TP[3:0] PE14TN[3:0] PE15RP[3:0] PE15RN[3:0] PE15TP[3:0] PE15TN[3:0] REFCLKM Type I O I Name/Description PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pairs for port 8. PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pairs for port 8. PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pairs for port 9. When port 8 is merged with port 9, these signals become port 8 receive pairs for lanes 4 through 7. PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pairs for port 9. When port 8 is merged with port 9, these signals become port 8 transmit pairs for lanes 4 through 7. PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pairs for port 10. PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pairs for port 10. PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pairs for port 11. When port 10 is merged with port 11, these signals become port 10 receive pairs for lanes 4 through 7. PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pairs for port 11. When port 10 is merged with port 11, these signals become port 10 transmit pairs for lanes 4 through 7. PCI Express Port 12 Serial Data Receive. Differential PCI Express receive pairs for port 12. PCI Express Port 12 Serial Data Transmit. Differential PCI Express transmit pairs for port 12. PCI Express Port 13 Serial Data Receive. Differential PCI Express receive pairs for port 13. When port 12 is merged with port 13, these signals become port 12 receive pairs for lanes 4 through 7. PCI Express Port 13 Serial Data Transmit. Differential PCI Express transmit pairs for port 13. When port 12 is merged with port 13, these signals become port 12 transmit pairs for lanes 4 through 7. PCI Express Port 14 Serial Data Receive. Differential PCI Express receive pairs for port 14. PCI Express Port 14 Serial Data Transmit. Differential PCI Express transmit pairs for port 14. PCI Express Port 15 Serial Data Receive. Differential PCI Express receive pairs for port 15. When port 14 is merged with port 15, these signals become port 14 receive pairs for lanes 4 through 7. PCI Express Port 15 Serial Data Transmit. Differential PCI Express transmit pairs for port 15. When port 14 is merged with port 15, these signals become port 14 transmit pairs for lanes 4 through 7. PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. Table 2 PCI Express Interface Pins (Part 2 of 2) O I O I O I O I O I O I O I PEREFCLKP[3:0] PEREFCLKN[3:0] I 5 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal MSMBADDR[4:1] MSMBCLK Type I I/O Name/Description Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT I/O I I/O I/O Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] Type I/O I/O I/O I/O I/O I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 Table 4 General Purpose I/O Pins (Part 1 of 4) GPIO[6] I/O GPIO[7] I/O GPIO[8] I/O 6 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal GPIO[9] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P7RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 7 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P8RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 8 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P9RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 9 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P10RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 10 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P11RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 11 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P12RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 12 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P13RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 13 Table 4 General Purpose I/O Pins (Part 2 of 4) GPIO[10] I/O GPIO[11] I/O GPIO[12] I/O GPIO[13] I/O GPIO[14] I/O GPIO[15] I/O GPIO[16] I/O GPIO[17] I/O GPIO[18] I/O 7 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal GPIO[19] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P14RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 14 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P15RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 15 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 0 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 1 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 2 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN3 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 3 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN4 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 4 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN5 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 5 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN6 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 6 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN7 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 7 Table 4 General Purpose I/O Pins (Part 3 of 4) GPIO[20] I/O GPIO[21] I/O GPIO[22] I/O GPIO[23] I/O GPIO[24] I/O GPIO[25] I/O GPIO[26] I/O GPIO[27] I/O GPIO[28] I/O 8 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal GPIO[29] GPIO[30] GPIO[31] Type I/O I/O I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN10 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 10 Table 4 General Purpose I/O Pins (Part 4 of 4) Signal CCLKDS Type I Name/Description Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port. Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with port 0 to form a single x8 port. The SerDes lanes associated with port B become lanes 4 through 7 of port 0. Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with port 2 to form a single x8 port. The SerDes lanes associated with port D become lanes 4 through 7 of port 2. Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with port 4 to form a single x8 port. The SerDes lanes associated with port F become lanes 4 through 7 of port 4. Port 6 and 7 Merge. When this pin is asserted, port 7 is merged with port 6 to form a single x8 port. The SerDes lanes associated with port H become lanes 4 through 7 of port 6. Port 8 and 9 Merge. When this pin is asserted, port 9 is merged with port 8 to form a single x8 port. The SerDes lanes associated with port H become lanes 4 through 7 of port 8. Port 10 and 11 Merge. When this pin is asserted, port 11 is merged with port 10 to form a single x8 port. The SerDes lanes associated with port H become lanes 4 through 7 of port 10. Port 12 and 13 Merge. When this pin is asserted, port 13 is merged with port 12 to form a single x8 port. The SerDes lanes associated with port H become lanes 4 through 7 of port 12. Port 14 and 15 Merge. When this pin is asserted, port 15 is merged with port 14 to form a single x8 port. The SerDes lanes associated with port H become lanes 4 through 7 of port 14. Table 5 System Pins (Part 1 of 2) CCLKUS MSMBSMODE P01MERGEN I I I P23MERGEN I P45MERGEN I P67MERGEN I P89MERGEN I P1011MERGEN I P1213MERGEN I P1415MERGEN I 9 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal PERSTN RSTHALT Type I I Name/Description Fundamental Reset. Assertion of this signal resets all logic inside the PES64H16 and initiates a PCI Express fundamental reset. Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES64H16 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. Switch Mode. These configuration pins determine the PES64H16 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 through 0x7 - Reserved 0x8 - Normal switch mode with upstream port failover (port 0 selected as the upstream port) 0x9 - Normal switch mode with upstream port failover (port 2 selected as the upstream port) 0xA - Normal switch mode with Serial EEPROM initialization and upstream port failover (port 0 selected as the upstream port) 0xB - Normal switch mode with Serial EEPROM initialization and upstream port failover (port 2 selected as the upstream port) 0xC through 0xF - Reserved Table 5 System Pins (Part 2 of 2) SWMODE[3:0] I Signal JTAG_TCK Type I Name/Description JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N I O I I Signal VDDCORE VDDIO VDDPE Type I I I Name/Description Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. Table 7 Power and Ground Pins 10 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal VDDAPE VSS VTTPE Type I I Name/Description PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. Ground. PCI Express Serial Data Transmit Termination Voltage. This pin allows the driver termination voltage to be set, enabling the system designer to control the Common Mode Voltage and output voltage swing of the corresponding PCI Serial Data Transmit differential pair. Table 7 Power and Ground Pins 11 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin Characteristics Note: Some input pads of the PES64H16 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function PCI Express Interface Pin Name PE0RN[3:0] PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE1RN[3:0] PE1RP[3:0] PE1TN[3:0] PE1TP[3:0] PE2RN[3:0] PE2RP[3:0] PE2TN[3:0] PE2TP[3:0] PE3RN[3:0] PE3RP[3:0] PE3TN[3:0] PE3TP[3:0] PE4RN[3:0] PE4RP[3:0] PE4TN[3:0] PE4TP[3:0] PE5RN[3:0] PE5RP[3:0] PE5TN[3:0] PE5TP[3:0] PE6RN[3:0] PE6RP[3:0] PE6TN[3:0] PE6TP[3:0] PE7RN[3:0] PE7RP[3:0] PE7TN[3:0] PE7TP[3:0] PE8RN[3:0] Type I I O O I I O O I I O O I I O O I I O O I I O O I I O O I I O O I Buffer CML I/O Type Serial Link Internal Resistor Notes Table 8 Pin Characteristics (Part 1 of 3) 12 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Function PCI Express Interface (cont.) Pin Name PE8RP[3:0] PE8TN[3:0] PE8TP[3:0] PE9RN[3:0] PE9RP[3:0] PE9TN[3:0] PE9TP[3:0] PE10RN[3:0] PE10RP[3:0] PE10TN[3:0] PE10TP[3:0] PE11RN[3:0] PE11RP[3:0] PE11TN[3:0] PE11TP[3:0] PE12RN[3:0] PE12RP[3:0] PE12TN[3:0] PE12TP[3:0] PE13RN[3:0] PE13RP[3:0] PE13TN[3:0] PE13TP[3:0] PE14RN[3:0] PE14RP[3:0] PE14TN[3:0] PE14TP[3:0] PE15RN[3:0] PE15RP[3:0] PE15TN[3:0] PE15TP[3:0] PEREFCLKN[3:0] PEREFCLKP[3:0] REFCLKM Type I O O I I O O I I O O I I O O I I O O I I O O I I O O I I O O I I I LVPECL/ CML LVTTL Diff. Clock Input Input pull-down Refer to Table 9 Buffer CML I/O Type Serial Link Internal Resistor Notes Table 8 Pin Characteristics (Part 2 of 3) 13 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Function SMBus Pin Name MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT General Purpose I/O System Pins GPIO[31:0] CCLKDS CCLKUS MSMBSMODE P01MERGEN P23MERGEN P45MERGEN P67MERGEN P89MERGEN P1011MERGEN P1213MERGEN P1415MERGEN PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 1. Type I I/O I/O I I/O I/O I/O I I I I I I I I I I I I I I I I O I I Buffer LVTTL I/O Type 1 Internal Resistor pull-up Notes STI STI pull-up STI STI LVTTL LVTTL Input pull-up pull-up pull-up pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down LVTTL STI STI STI STI pull-up pull-up pull-up pull-up External pull-down Schmitt Trigger Input (STI). Table 8 Pin Characteristics (Part 3 of 3) 14 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Logic Diagram -- PES64H16 PEREFCLKP[3:0] PEREFCLKN[3:0] REFCLKM 4 4 Reference Clock PCI Express Switch SerDes Input Port 0 ... PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PE1RP[0] PE1RN[0] PE1RP[3] PE1RN[3] PE2RP[0] PE2RN[0] PE2RP[3] PE2RN[3] PE3RP[0] PE3RN[0] PE3RP[3] PE3RN[3] PE0TP[0] PE0TN[0] PE0TP[3] PE0TN[3] PE1TP[0] PE1TN[0] PE1TP[3] PE1TN[3] PE2TP[0] PE2TN[0] PCI Express Switch SerDes Output Port 0 ... PCI Express Switch SerDes Input Port 1 PCI Express Switch SerDes Output Port 1 ... ... PCI Express Switch SerDes Input Port 2 PE2TP[3] PE2TN[3] PE3TP[0] PE3TN[0] PE3TP[3] PE3TN[3] PCI Express Switch SerDes Output Port 2 ... ... PCI Express Switch SerDes Input Port 3 PCI Express Switch SerDes Output Port 3 ... ... ... ... PES64H16 PCI Express Switch SerDes Input Port 15 ... PE15RP[0] PE15RN[0] PE15RP[3] PE15RN[3] PE15TP[0] PE15TN[0] PE15TP[3] PE15TN[3] PCI Express Switch SerDes Output Port 15 ... Master SMBus Interface MSMBADDR[4:1] MSMBCLK MSMBDAT 4 4 SSMBADDR[5,3:1] SSMBCLK SSMBDAT Slave SMBus Interface General Purpose I/O 32 GPIO[31:0] System Pins MSMBSMODE CCLKDS CCLKUS RSTHALT PERSTN SWMODE[3:0] P01MERGEN P23MERGEN P45MERGEN P67MERGEN P89MERGEN P1011MERGEN P1213MERGEN P1415MERGEN 4 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VDDCORE VDDIO VDDPE VDDAPE VSS VTTPE Power/Ground Figure 4 PES64H16 Logic Diagram 15 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter PEREFCLK RefclkFREQ RefclkDC2 TR, TF VSW Tjitter 1. The input clock 2. 3. Description Min Typical Max 1251 Unit Input reference clock frequency range Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing4 Input clock jitter (cycle-to-cycle) 100 40 0.6 50 MHz % RCUI3 V ps 60 0.2*RCUI 1.6 125 Table 9 Input Clock Requirements frequency will be either 100 or 125 MHz depending on signal REFCLKM. ClkIn must be AC coupled. Use 0.01 -- 0.1 F ceramic capacitors. RCUI (Reference Clock Unit Interval) refers to the reference clock period. coupling required. 4. AC AC Timing Characteristics Parameter PCIe Transmit UI TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER Description Min1 Typical1 Max1 Units Unit Interval Minimum Tx Eye Width Maximum time between the jitter median and maximum deviation from the median D+ / D- Tx output rise/fall time Minimum time in idle Maximum time to transition to a valid Idle after sending an Idle ordered set Maximum time to transition from valid idle to diff data Transmitter data skew between any 2 lanes 399.88 0.7 400 .9 400.12 ps UI 0.15 50 50 20 20 500 1300 90 UI ps UI UI UI ps TTX-RISE, TTX-FALL TTX- IDLE-MIN TTX-IDLE-SET-TOIDLE TTX-IDLE-TO-DIFFDATA TTX-SKEW PCIe Receive UI TRX-EYE (with jitter) TRX-EYE-MEDIUM TO MAX JITTER Unit Interval Minimum Receiver Eye Width (jitter tolerance) Max time between jitter median & max deviation Unexpected Idle Enter Detect Threshold Integration Time Lane to lane input skew 399.88 0.4 400 400.12 ps UI 0.3 10 20 UI ms ns TRX-IDLE-DET-DIFFENTER TIME TRX-SKEW Table 10 PCIe AC Timing Characteristics 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 16 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal GPIO GPIO[31:0]1 Symbol Reference Edge Min Max Unit Timing Diagram Reference Tpw_13b2 None 50 -- ns See Figure 5. Table 11 GPIO AC Timing Characteristics 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. EXTCLK Tpw_13b GPIO (asynchronous input) Figure 5 GPIO AC Timing Waveform Signal Symbol Reference Edge Min Max Unit Timing Diagram Referenc e JTAG JTAG_TCK Tper_16a Thigh_16a, Tlow_16a JTAG_TMS1, JTAG_TDI JTAG_TDO JTAG_TRST_N 1. none 50.0 10.0 -- 25.0 -- -- 20 20 -- ns ns ns ns ns ns ns See Figure 6. Tsu_16b Thld_16b Tdo_16c Tdz_16c2 Tpw_16d2 JTAG_TCK rising JTAG_TCK falling none 2.4 1.0 -- -- 25.0 Table 12 JTAG AC Timing Characteristics The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. The values for this symbol were determined by calculation, not by testing. 2. 17 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 6 JTAG AC Timing Waveform Tdz_16c Tper_16a Recommended Operating Supply Voltages Symbol VDDCORE VDDI/O VDDPE VDDAPE VTTPE VSS Parameter Internal logic supply I/O supply except for SerDes LVPECL/CML PCI Express Digital Power PCI Express Analog Power PCI Express Serial Data Transmit Termination Voltage Common ground Minimum 0.9 3.0 0.9 0.9 1.425 0 Table 13 PES64H16 Operating Voltages Typical 1.0 3.3 1.0 1.0 1.5 0 Maximum 1.1 3.6 1.1 1.1 1.575 0 Unit V V V V V V Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES64H16, the power-up sequence must be as follows: 1. VDDI/O -- 3.3V 2. VDDCore, VDDPE, VDDAPE -- 1.0V 3. VTTPE -- 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the power-up sequence. 18 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Recommended Operating Temperature Grade Commercial Industrial Temperature 0C to +70C Ambient -40C to +85C Ambient Table 14 PES64H16 Operating Temperatures Power Consumption Typical power is measured under the following conditions: 25C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Core Supply Typ 1.0V Max 1.1V PCIe Digital Supply Typ 1.0V Max 1.1V PCIe Analog Supply Typ 1.0V Max 1.1V PCIe Termination Supply Typ 1.5V Max 1.575V I/O Supply Typ 3.3V Max 3.6V Total Typ Power Max Power Number of active Lanes per Port 8/8/8/8/8/8/8/8 mA Watts 2900 2.9 3600 3.96 2892 2.89 3470 3.81 1157 1.16 1500 1.65 1482 2.22 2000 3.15 5 0.018 5 0.02 9.18W 12.57W Table 15 PES64H16 Power Consumption 19 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Thermal Considerations This section describes thermal considerations for the PES64H16 (35mm2 FCBGA1156 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES64H16 switch. Symbol TJ(max) TA(max) JC P Parameter Junction Temperature Ambient Temperature Thermal Resistance, Junction-to-Case Power Dissipation of the Device Value 125 70 0.2 12.57 Units o o o Conditions Maximum Maximum Maximum C C C/W Watts Table 16 Thermal Specifications for PES64H16, 35x35 mm FCBGA1156 Package Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 16. Consequently, the effective junction to ambient thermal resistance (JA) for the worst case scenario must be maintained below the value determined by the formula: JA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired JA becomes a known entity to the system designer. How to achieve the desired JA is left up to the board or system designer, but in general, it can be achieved by adding the effects of JC (value provided in Table 16), thermal resistance of the chosen adhesive (CS), that of the heat sink (SA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 10 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 1 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. 20 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. Min1 Typ1 Max1 I/O Type Serial Link Parameter PCIe Transmit VTX-DIFFp-p VTX-DE-RATIO VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta Description Unit Conditions Differential peak-to-peak output voltage De-emphasized differential output voltage DC Common mode voltage RMS AC peak common mode output voltage Abs delta of DC common mode voltage between L0 and idle Abs delta of DC common mode voltage between D+ and DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss Transmitter Common Mode Return loss DC Differential TX impedance Single ended TX Impedance TX Eye Height (De-emphasized bits) TX Eye Height (Transition bits) 800 -3 -0.1 1 1200 -4 3.7 20 100 25 20 600 mV dB V mV mV mV mV mV dB dB VTX-CM-DC-linedelta VTX-Idle-DiffP VTX-RCV-Detect RLTX-DIFF RLTX-CM ZTX-DEFF-DC ZOSE Transmitter Eye Diagram Transmitter Eye Diagram PCIe Receive VRX-DIFFp-p VRX-CM-AC RLRX-DIFF RLRX-CM ZRX-DIFF-DC ZRX-COMM-DC 12 6 80 40 505 800 100 50 650 950 120 60 mV mV Differential input voltage (peak-to-peak) Receiver common-mode voltage for AC coupling Receiver Differential Return Loss Receiver Common Mode Return Loss Differential input impedance (DC) Single-ended input impedance 175 1200 150 mV mV dB dB 15 6 80 40 200k 65 100 50 350k 175 120 60 mV ZRX-COMM-HIGH- Powered down input common mode impedance (DC) Z-DC VRX-IDLE-DETDIFFp-p Electrical idle detect threshold PCIe REFCLK CIN Input Capacitance 1.5 -- pF Table 17 DC Electrical Characteristics (Part 1 of 2) 21 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet I/O Type Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) Input IOL IOH IOL IOH VIL VIH VIL VIH Capacitance Leakage CIN Inputs I/OLEAK W/O Pull-ups/downs I/OLEAK WITH Pull-ups/downs 1. Parameter Description Min1 Typ1 Max1 Unit Conditions -- -- -- -- -0.3 2.0 -0.3 2.0 -- -- -- -- 2.5 -5.5 12.0 -20.0 -- -- -- -- -- -- -- -- -- -- -- -- 0.8 VDDIO + 0.5 0.8 VDDIO + 0.5 8.5 + 10 + 10 + 80 mA mA mA mA V V V V pF VOL = 0.4v VOH = 1.5V VOL = 0.4v VOH = 1.5V -- -- -- -- -- VDDI/O (max) VDDI/O (max) VDDI/O (max) A A A Table 17 DC Electrical Characteristics (Part 2 of 2) Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. 22 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Package Pinout -- 1156-BGA Signal Pinout for PES64H16 The following table lists the pin numbers and signal names for the PES64H16 device. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 VSS VSS GPIO_19 VDDIO VSS PE9TP03 PE9TP02 VSS PE9TP01 PE9TP00 VSS PE8TP03 PE8TP02 VSS PE8TP01 PE8TP00 VSS PE3TP03 PE3TP02 VSS PE3TP01 PE3TP00 VSS PE2TP03 PE2TP02 VSS PE2TP01 PE2TP00 VSS VDDIO MSMBADDR_1 MSMBSMODE VSS VSS 1 Function Alt Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 VSS VDDIO GPIO_18 GPIO_17 VSS PE9TN03 PE9TN02 VSS PE9TN01 PE9TN00 VSS PE8TN03 PE8TN02 VSS PE8TN01 PE8TN00 VSS PE3TN03 PE3TN02 VSS PE3TN01 PE3TN00 VSS PE2TN03 PE2TN02 VSS PE2TN01 PE2TN00 VSS MSMBADDR_3 MSMBADDR_2 PERSTN VDDIO VSS 1 1 Function Alt Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 Function GPIO_29 GPIO_27 GPIO_21 GPIO_16 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MSMBADDR_4 JTAG_TDI JTAG_TRST_N SSMBADDR_2 SSMBADDR_1 1 1 1 Alt Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 Function GPIO_28 GPIO_26 VDDIO GPIO_23 VSS PE9RP03 PE9RP02 VSS PE9RP01 PE9RP00 VSS PE8RP03 PE8RP02 VSS PE8RP01 PE8RP00 VSS PE3RP03 PE3RP02 VSS PE3RP01 PE3RP00 VSS PE2RP03 PE2RP02 VSS PE2RP01 PE2RP00 VSS JTAG_TMS VDDIO SSMBADDR_5 SSMBADDR_3 VDDIO 1 Alt 1 1 Table 18 PES64H16 1156-pin Signal Pin-Out (Part 1 of 9) 23 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 Function VDDIO GPIO_30 GPIO_31 GPIO_24 VSS PE9RN03 PE9RN02 VSS PE9RN01 PE9RN00 VSS PE8RN03 PE8RN02 VSS PE8RN01 PE8RN00 VSS PE3RN03 PE3RN02 VSS PE3RN01 PE3RN00 VSS PE2RN03 PE2RN02 VSS PE2RN01 PE2RN00 VSS VSS VSS VSS VSS VSS 1 1 Alt Pin F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PE1RN03 PE1RP03 VSS PE1TN03 PE1TP03 Function Alt Pin G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 Function PE10TP00 PE10TN00 VSS PE10RP00 PE10RN00 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PEREFCLKP1 PEREFCLKN1 VSS VSS VSS VSS VSS VSS VSS VSS MSMBCLK VSS VSS PE1RN02 PE1RP02 VSS PE1TN02 PE1TP02 Alt Pin H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 Function PE10TP01 PE10TN01 VSS PE10RP01 PE10RN01 VSS VSS GPIO_20 VDDIO VSS VSS VSS VTTPE VSS VDDAPE VSS VSS VSS VSS VDDAPE VSS VTTPE VSS VSS VSS MSMBDAT VDDIO SSMBCLK VSS VSS VSS VSS VSS VSS 1 Alt Table 18 PES64H16 1156-pin Signal Pin-Out (Part 2 of 9) 24 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 VSS VSS VSS VSS VSS VSS VSS VSS GPIO_25 VSS VSS VSS VSS VDDPE VSS VSS VTTPE VTTPE VSS VSS VDDPE VSS VSS VSS JTAG_TDO VDDIO SSMBDAT VSS VSS PE1RN01 PE1RP01 VSS PE1TN01 PE1TP01 1 Function Alt Pin K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 Function PE10TP02 PE10TN02 VSS PE10RP02 PE10RN02 VSS VSS VSS VDDIO GPIO_22 VSS VSS VTTPE VSS VDDAPE VSS VTTPE VTTPE VSS VDDAPE VSS VTTPE VSS VSS CCLKDS JTAG_TCK VSS VSS VSS PE1RN00 PE1RP00 VSS PE1TN00 PE1TP00 1 Alt Pin L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 L34 Function PE10TP03 PE10TN03 VSS PE10RP03 PE10RN03 VSS VSS VSS VSS VSS VSS VSS VDDPE VDDPE VDDPE VSS VDDPE VDDPE VSS VDDPE VDDPE VDDPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Alt Pin M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDPE VSS VDDPE VSS VDDPE VDDPE VSS VDDPE VSS VDDPE VSS VSS VSS VSS VSS VSS VSS PE0RN03 PE0RP03 VSS PE0TN03 PE0TP03 Function Alt Table 18 PES64H16 1156-pin Signal Pin-Out (Part 3 of 9) 25 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 N32 N33 N34 Function PE11TP00 PE11TN00 VSS PE11RP00 PE11RN00 VSS VSS VTTPE VSS VTTPE VDDPE VDDPE VDDCORE VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VDDCORE VDDCORE VDDPE VDDPE VTTPE VSS VTTPE VSS VSS PE0RN02 PE0RP02 VSS PE0TN02 PE0TP02 Alt Pin P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 Function PE11TP01 PE11TN01 VSS PE11RP01 PE11RN01 VSS VSS VSS VDDPE VSS VDDPE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VSS VDDPE VSS VDDPE VSS VSS VSS VSS VSS VSS VSS VSS Alt Pin R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 VSS VSS VSS VSS VSS VSS VSS VDDAPE VSS VDDAPE VDDPE VDDPE VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDPE VDDPE VDDAPE VSS VDDAPE VSS VSS PE0RN01 PE0RP01 VSS PE0TN01 PE0TP01 Function Alt Pin T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 Function PE11TP02 PE11TN02 VSS PE11RP02 PE11RN02 VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VSS VSS VSS VSS VSS VSS VSS PE0RN00 PE0RP00 VSS PE0TN00 PE0TP00 Alt Table 18 PES64H16 1156-pin Signal Pin-Out (Part 4 of 9) 26 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 Function PE11TP03 PE11TN03 VSS PE11RP03 PE11RN03 VSS PEREFCLKN2 VSS VTTPE VTTPE VDDPE VDDPE VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VSS VDDPE VDDPE VTTPE VTTPE VSS PEREFCLKP0 VSS VSS VSS VSS VSS VSS Alt Pin V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 VSS VSS VSS VSS VSS VSS PEREFCLKP2 VSS VTTPE VTTPE VDDPE VDDPE VSS VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VDDPE VDDPE VTTPE VTTPE VSS PEREFCLKN0 VSS PE15RN03 PE15RP03 VSS PE15TN03 PE15TP03 Function Alt Pin W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W33 W34 Function PE4TP00 PE4TN00 VSS PE4RP00 PE4RN00 VSS VSS VSS VSS VSS VSS VSS VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS PE15RN02 PE15RP02 VSS PE15TN02 PE15TP02 Alt Pin Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Function PE4TP01 PE4TN01 VSS PE4RP01 PE4RN01 VSS VSS VDDAPE VSS VDDAPE VDDPE VDDPE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VDDPE VDDPE VDDAPE VSS VDDAPE VSS VSS VSS VSS VSS VSS VSS Alt Table 18 PES64H16 1156-pin Signal Pin-Out (Part 5 of 9) 27 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 VSS VSS VSS VSS VSS VSS VSS VSS VDDPE VSS VDDPE VSS VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDPE VSS VDDPE VSS VSS VSS PE15RN01 PE15RP01 VSS PE15TN01 PE15TP01 Function Alt Pin AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34 Function PE4TP02 PE4TN02 VSS PE4RP02 PE4RN02 VSS VSS VTTPE VSS VTTPE VDDPE VDDPE VDDCORE VDDCORE VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VDDCORE VDDPE VDDPE VTTPE VSS VTTPE VSS VSS PE15RN00 PE15RP00 VSS PE15TN00 PE15TP00 Alt Pin AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 Function PE4TP03 PE4TN03 VSS PE4RP03 PE4RN03 VSS VSS VSS VSS VSS VSS VSS VDDPE VSS VDDPE VSS VDDPE VDDPE VSS VDDPE VSS VDDPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Alt Pin AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDPE VDDPE VDDPE VSS VDDPE VDDPE VSS VDDPE VDDPE VDDPE VSS VSS VSS VSS VSS VSS VSS PE14RN03 PE14RP03 VSS PE14TN03 PE14TP03 Function Alt Table 18 PES64H16 1156-pin Signal Pin-Out (Part 6 of 9) 28 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 Function PE5TP00 PE5TN00 VSS PE5RP00 PE5RN00 VSS VSS VSS VDDIO VDDIO VSS VSS VTTPE VSS VDDAPE VSS VTTPE VTTPE VSS VDDAPE VSS VTTPE VSS VSS GPIO_06 VDDIO VSS VSS VSS PE14RN02 PE14RP02 VSS PE14TN02 PE14TP02 1 Alt Pin AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 Function PE5TP01 PE5TN01 VSS PE5RP01 PE5RN01 VSS VSS VSS VDDIO VDDIO VSS VSS VSS VDDPE VSS VSS VTTPE VTTPE VSS VSS VDDPE VSS VSS VSS VSS GPIO_09 VSS VSS VSS VSS VSS VSS VSS VSS 1 Alt Pin AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 VSS VSS VSS VSS VSS VSS CCLKUS VDDIO VDDIO VSS VSS VSS VTTPE VSS VDDAPE VSS VSS VSS VSS VDDAPE VSS VTTPE VSS VSS VSS VDDIO GPIO_04 VSS VSS PE14RN01 PE14RP01 VSS PE14TN01 PE14TP01 Function Alt Pin AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 Function PE5TP02 PE5TN02 VSS PE5RP02 PE5RN02 VSS VSS REFCLKM VSS VSS VSS VSS VSS VSS VSS VSS PEREFCLKN3 PEREFCLKP3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PE14RN00 PE14RP00 VSS PE14TN00 PE14TP00 Alt Table 18 PES64H16 1156-pin Signal Pin-Out (Part 7 of 9) 29 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 Function PE5TP03 PE5TN03 VSS PE5RP03 PE5RN03 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Alt Pin AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 VSS VSS VSS VSS VSS VSS PE6RN00 PE6RN01 VSS PE6RN02 PE6RN03 VSS PE7RN00 PE7RN01 VSS PE7RN02 PE7RN03 VSS PE12RN00 PE12RN01 VSS PE12RN02 PE12RN03 VSS PE13RN00 PE13RN01 VSS PE13RN02 PE13RN03 VSS GPIO_08 GPIO_15 GPIO_14 VDDIO 1 1 1 Function Alt Pin AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 Function VDDIO P01MERGEN P45MERGEN VDDIO P89MERGEN VSS PE6RP00 PE6RP01 VSS PE6RP02 PE6RP03 VSS PE7RP00 PE7RP01 VSS PE7RP02 PE7RP03 VSS PE12RP00 PE12RP01 VSS PE12RP02 PE12RP03 VSS PE13RP00 PE13RP01 VSS PE13RP02 PE13RP03 VSS GPIO_07 VDDIO GPIO_10 GPIO_12 1 1 1 Alt Pin AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 Function P23MERGEN P67MERGEN P1415MERGEN P1011MERGEN SWMODE_3 VSS VSS VSS VSS Alt AM10 VSS AM11 VSS AM12 VSS AM13 VSS AM14 VSS AM15 VSS AM16 VSS AM17 VSS AM18 VSS AM19 VSS AM20 VSS AM21 VSS AM22 VSS AM23 VSS AM24 VSS AM25 VSS AM26 VSS AM27 VSS AM28 VSS AM29 VSS AM30 VSS AM31 GPIO_00 AM32 GPIO_05 AM33 GPIO_11 AM34 GPIO_13 1 1 1 Table 18 PES64H16 1156-pin Signal Pin-Out (Part 8 of 9) 30 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Pin AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 VSS VDDIO P1213MERGEN SWMODE_0 SWMODE_2 VSS PE6TN00 PE6TN01 VSS PE6TN02 PE6TN03 VSS PE7TN00 PE7TN01 VSS PE7TN02 PE7TN03 Function Alt Pin AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 VSS PE12TN00 PE12TN01 VSS PE12TN02 PE12TN03 VSS PE13TN00 PE13TN01 VSS PE13TN02 PE13TN03 VSS GPIO_01 GPIO_02 VDDIO VSS Function Alt Pin AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 VSS VSS RSTHALT SWMODE_1 VDDIO VSS PE6TP00 PE6TP01 VSS PE6TP02 PE6TP03 VSS PE7TP00 PE7TP01 VSS PE7TP02 PE7TP03 Function Alt Pin AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 VSS PE12TP00 PE12TP01 VSS PE12TP02 PE12TP03 VSS PE13TP00 PE13TP01 VSS PE13TP02 PE13TP03 VSS VDDIO GPIO_03 VSS VSS Function Alt Table 18 PES64H16 1156-pin Signal Pin-Out (Part 9 of 9) Alternate Signal Functions Pin AM32 AE25 AL31 AK31 AF26 AL33 AM33 AL34 AM34 AK33 AK32 C4 B4 GPIO GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 Alternate GPEN P1RSTN P2RSTN P3RSTN P4RSTN P5RSTN P6RSTN P7RSTN P8RSTN P9RSTN P10RSTN P11RSTN P12RSTN Pin B3 A3 H8 C3 K10 D4 E4 J9 D2 C2 D1 E3 -- GPIO GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_31 -- Alternate P13RSTN P14RSTN P15RSTN IOEXPINTN0 IOEXPINTN1 IOEXPINTN2 IOEXPINTN3 IOEXPINTN4 IOEXPINTN5 IOEXPINTN6 IOEXPINTN7 IOEXPINTN10 -- Table 19 PES64H16 Alternate Signal Functions 31 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Power Pins VDDCore N13 N14 N15 N17 N19 N20 N21 N22 P13 P15 P17 P19 P21 P22 R13 R14 R16 R18 R20 R22 T15 T17 T19 T21 T22 U13 U14 U16 U18 U20 V15 V17 VDDCore V19 V21 V22 W13 W14 W16 W18 W20 Y13 Y15 Y17 Y19 Y21 Y22 AA13 AA14 AA16 AA18 AA20 AA22 AB13 AB14 AB15 AB16 AB18 AB20 AB21 AB22 VDDIO A4 A30 B2 B33 D3 D31 D34 E1 H9 H27 J26 K9 AE9 AE10 AE26 AF9 AF10 AG8 AG9 AG26 AK34 AL1 AL4 AL32 AN2 AN33 AP5 AP31 VDDPE J14 J21 L13 L14 L15 L17 L18 L20 L21 L22 M13 M15 M17 M18 M20 M22 N11 N12 N23 N24 P9 P11 P24 P26 R11 R12 R23 R24 U11 U12 U23 U24 VDDPE V11 V12 V23 V24 Y11 Y12 Y23 Y24 AA9 AA11 AA24 AA26 AB11 AB12 AB23 AB24 AC13 AC15 AC17 AC18 AC20 AC22 AD13 AD14 AD15 AD17 AD18 AD20 AD21 AD22 AF14 AF21 VDDAPE H15 H20 K15 K20 R8 R10 R25 R27 Y8 Y10 Y25 Y27 AE15 AE20 AG15 AG20 VTTPE H13 H22 J17 J18 K13 K17 K18 K22 N8 N10 N25 N27 U9 U10 U25 U26 V9 V10 V25 V26 AB8 AB10 AB25 AB27 AE13 AE17 AE18 AE22 AF17 AF18 AG13 AG22 Table 20 PES64H16 Power Pins 32 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Ground Pins VSS A1 A2 A5 A8 A11 A14 A17 A20 A23 A26 A29 A33 A34 B1 B5 B8 B11 B14 B17 B20 B23 B26 B29 B34 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 VSS C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 D5 D8 D11 D14 D17 D20 D23 D26 D29 E5 E8 E11 E14 E17 E20 E23 E26 E29 E30 E31 E32 VSS E33 E34 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F32 G3 G6 G7 VSS G8 G9 G10 G11 G12 G13 G14 G15 G16 G19 G20 G21 G22 G23 G24 G25 G26 G28 G29 G32 H3 H6 H7 H10 H11 H12 H14 H16 H17 H18 H19 H21 H23 H24 H25 VSS H29 H30 H31 H32 H33 H34 J1 J2 J3 J4 J5 J6 J7 J8 J10 J11 J12 J13 J15 J16 J19 J20 J22 J23 J24 J28 J29 J32 K3 K6 K7 K8 K11 K12 K14 VSS K16 K19 K21 K23 K24 K27 K28 K29 K32 L3 L6 L7 L8 L9 L10 L11 L12 L16 L19 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 L34 M1 M2 M3 M4 VSS M5 M6 M7 M8 M9 M10 M11 M12 M14 M16 M19 M21 M23 M24 M25 M26 M27 M28 M29 M32 N3 N6 N7 N9 N16 N18 N26 N28 N29 N32 P3 P6 P7 P8 P10 VSS P12 P14 P16 P18 P20 P23 P25 P27 P28 P29 P30 P31 P32 P33 P34 R1 R2 R3 R4 R5 R6 R7 R9 R15 R17 R19 R21 R26 R28 R29 R32 T3 T6 T7 T8 Table 21 PES64H16 Ground Pins (Part 1 of 3) 33 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet VSS T9 T10 T11 T12 T13 T14 T16 T18 T20 T23 T24 T25 T26 T27 T28 T29 T32 U3 U6 U8 U15 U17 U19 U21 U22 U27 U29 U30 U31 U32 U33 U34 V1 V2 V3 V4 V5 VSS V6 V8 V13 V14 V16 V18 V20 V27 V29 V32 W3 W6 W7 W8 W9 W10 W11 W12 W15 W17 W19 W21 W22 W23 W24 W25 W26 W27 W28 W29 W32 Y3 Y6 Y7 Y9 Y14 Y16 VSS Y18 Y20 Y26 Y28 Y29 Y30 Y31 Y32 Y33 Y34 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA10 AA12 AA15 AA17 AA19 AA21 AA23 AA25 AA27 AA28 AA29 AA32 AB3 AB6 AB7 AB9 AB17 AB19 AB26 VSS AB28 AB29 AB32 AC3 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC14 AC16 AC19 AC21 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 VSS AD11 AD12 AD16 AD19 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD32 AE3 AE6 AE7 AE8 AE11 AE12 AE14 AE16 AE19 AE21 AE23 AE24 AE27 AE28 AE29 AE32 AF3 AF6 AF7 AF8 AF11 AF12 AF13 AF15 AF16 VSS AF19 AF20 AF22 AF23 AF24 AF25 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AG1 AG2 AG3 AG4 AG5 AG6 AG10 AG11 AG12 AG14 AG16 AG17 AG18 AG19 AG21 AG23 AG24 AG25 AG28 AG29 AG32 AH3 AH6 VSS AH7 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH32 AJ3 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 VSS AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AK1 AK2 AK3 AK4 AK5 AK6 AK9 AK12 AK15 AK18 AK21 AK24 AK27 AK30 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 Table 21 PES64H16 Ground Pins (Part 2 of 3) 34 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet VSS AM6 AM7 AM8 AM9 AM10 AM11 AM12 VSS AM13 AM14 AM15 AM16 AM17 AM18 AM19 VSS AM20 AM21 AM22 AM23 AM24 AM25 AM26 VSS AM27 AM28 AM29 AM30 AN1 AN6 AN9 VSS AN12 AN15 AN18 AN21 AN24 AN27 AN30 VSS AN34 AP1 AP2 AP6 AP9 AP12 AP15 VSS AP18 AP21 AP24 AP27 AP30 AP33 AP34 VSS Table 21 PES64H16 Ground Pins (Part 3 of 3) Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 I/O Type I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location K25 AG7 AM31 AN31 AN32 AP32 AG27 AM32 AE25 AL31 AK31 AF26 AL33 AM33 AL34 AM34 AK33 AK32 C4 B4 B3 A3 H8 General Purpose I/O Signal Category System Table 22 89PES64H16 Alphabetical Signal List (Part 1 of 10) 35 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal Name GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE P01MERGEN P23MERGEN P45MERGEN P67MERGEN P89MERGEN P1011MERGEN P1213MERGEN P1415MERGEN PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 I/O Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O I I I I I I I/O I/O I I I I I I I I I I I I I I Location C3 K10 D4 E4 J9 D2 C2 D1 C1 E2 E3 K26 C31 J25 D30 C32 A31 B31 B30 C30 G27 H26 A32 AL2 AM1 AL3 AM2 AL5 AM4 AN3 AM3 T30 R30 N30 M30 T31 PCI Express System SMBus Interface Test Signal Category General Purpose I/O (cont.) Table 22 89PES64H16 Alphabetical Signal List (Part 2 of 10) 36 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal Name PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE1RN00 PE1RN01 PE1RN02 PE1RN03 PE1RP00 PE1RP01 PE1RP02 PE1RP03 PE1TN00 PE1TN01 PE1TN02 PE1TN03 PE1TP00 PE1TP01 PE1TP02 PE1TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 I/O Type I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O Location R31 N31 M31 T33 R33 N33 M33 T34 R34 N34 M34 K30 J30 G30 F30 K31 J31 G31 F31 K33 J33 G33 F33 K34 J34 G34 F34 E28 E27 E25 E24 D28 D27 D25 D24 B28 Signal Category PCI Express (cont.) Table 22 89PES64H16 Alphabetical Signal List (Part 3 of 10) 37 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal Name PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE3RN00 PE3RN01 PE3RN02 PE3RN03 PE3RP00 PE3RP01 PE3RP02 PE3RP03 PE3TN00 PE3TN01 PE3TN02 PE3TN03 PE3TP00 PE3TP01 PE3TP02 PE3TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 PE4RP02 PE4RP03 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 I/O Type O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O Location B27 B25 B24 A28 A27 A25 A24 E22 E21 E19 E18 D22 D21 D19 D18 B22 B21 B19 B18 A22 A21 A19 A18 W5 Y5 AB5 AC5 W4 Y4 AB4 AC4 W2 Y2 AB2 AC2 W1 Signal Category PCI Express (cont.) Table 22 89PES64H16 Alphabetical Signal List (Part 4 of 10) 38 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal Name PE4TP01 PE4TP02 PE4TP03 PE5RN00 PE5RN01 PE5RN02 PE5RN03 PE5RP00 PE5RP01 PE5RP02 PE5RP03 PE5TN00 PE5TN01 PE5TN02 PE5TN03 PE5TP00 PE5TP01 PE5TP02 PE5TP03 PE6RN00 PE6RN01 PE6RN02 PE6RN03 PE6RP00 PE6RP01 PE6RP02 PE6RP03 PE6TN00 PE6TN01 PE6TN02 PE6TN03 PE6TP00 PE6TP01 PE6TP02 PE6TP03 PE7RN00 I/O Type O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O O O O I Location Y1 AB1 AC1 AE5 AF5 AH5 AJ5 AE4 AF4 AH4 AJ4 AE2 AF2 AH2 AJ2 AE1 AF1 AH1 AJ1 AK7 AK8 AK10 AK11 AL7 AL8 AL10 AL11 AN7 AN8 AN10 AN11 AP7 AP8 AP10 AP11 AK13 Signal Category PCI Express (cont.) Table 22 89PES64H16 Alphabetical Signal List (Part 5 of 10) 39 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal Name PE7RN01 PE7RN02 PE7RN03 PE7RP00 PE7RP01 PE7RP02 PE7RP03 PE7TN00 PE7TN01 PE7TN02 PE7TN03 PE7TP00 PE7TP01 PE7TP02 PE7TP03 PE8RN00 PE8RN01 PE8RN02 PE8RN03 PE8RP00 PE8RP01 PE8RP02 PE8RP03 PE8TN00 PE8TN01 PE8TN02 PE8TN03 PE8TP00 PE8TP01 PE8TP02 PE8TP03 PE9RN00 PE9RN01 PE9RN02 PE9RN03 PE9RP00 I/O Type I I I I I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I Location AK14 AK16 AK17 AL13 AL14 AL16 AL17 AN13 AN14 AN16 AN17 AP13 AP14 AP16 AP17 E16 E15 E13 E12 D16 D15 D13 D12 B16 B15 B13 B12 A16 A15 A13 A12 E10 E9 E7 E6 D10 Signal Category PCI Express (cont.) Table 22 89PES64H16 Alphabetical Signal List (Part 6 of 10) 40 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal Name PE9RP01 PE9RP02 PE9RP03 PE9TN00 PE9TN01 PE9TN02 PE9TN03 PE9TP00 PE9TP01 PE9TP02 PE9TP03 PE10RN00 PE10RN01 PE10RN02 PE10RN03 PE10RP00 PE10RP01 PE10RP02 PE10RP03 PE10TN00 PE10TN01 PE10TN02 PE10TN03 PE10TP00 PE10TP01 PE10TP02 PE10TP03 PE11RN00 PE11RN01 PE11RN02 PE11RN03 PE11RP00 PE11RP01 PE11RP02 PE11RP03 PE11TN00 I/O Type I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O Location D9 D7 D6 B10 B9 B7 B6 A10 A9 A7 A6 G5 H5 K5 L5 G4 H4 K4 L4 G2 H2 K2 L2 G1 H1 K1 L1 N5 P5 T5 U5 N4 P4 T4 U4 N2 Signal Category PCI Express (cont.) Table 22 89PES64H16 Alphabetical Signal List (Part 7 of 10) 41 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal Name PE11TN01 PE11TN02 PE11TN03 PE11TP00 PE11TP01 PE11TP02 PE11TP03 PE12RN00 PE12RN01 PE12RN02 PE12RN03 PE12RP00 PE12RP01 PE12RP02 PE12RP03 PE12TN00 PE12TN01 PE12TN02 PE12TN03 PE12TP00 PE12TP01 PE12TP02 PE12TP03 PE13RN00 PE13RN01 PE13RN02 PE13RN03 PE13RP00 PE13RP01 PE13RP02 PE13RP03 PE13TN00 PE13TN01 PE13TN02 PE13TN03 PE13TP00 I/O Type O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O Location P2 T2 U2 N1 P1 T1 U1 AK19 AK20 AK22 AK23 AL19 AL20 AL22 AL23 AN19 AN20 AN22 AN23 AP19 AP20 AP22 AP23 AK25 AK26 AK28 AK29 AL25 AL26 AL28 AL29 AN25 AN26 AN28 AN29 AP25 Signal Category PCI Express (cont.) Table 22 89PES64H16 Alphabetical Signal List (Part 8 of 10) 42 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal Name PE13TP01 PE13TP02 PE13TP03 PE14RN00 PE14RN01 PE14RN02 PE14RN03 PE14RP00 PE14RP01 PE14RP02 PE14RP03 PE14TN00 PE14TN01 PE14TN02 PE14TN03 PE14TP00 PE14TP01 PE14TP02 PE14TP03 PE15RN00 PE15RN01 PE15RN02 PE15RN03 PE15RP00 PE15RP01 PE15RP02 PE15RP03 PE15TN00 PE15TN01 PE15TN02 PE15TN03 PE15TP00 PE15TP01 PE15TP02 PE15TP03 I/O Type O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O O O O Location AP26 AP28 AP29 AH30 AG30 AE30 AD30 AH31 AG31 AE31 AD31 AH33 AG33 AE33 AD33 AH34 AG34 AE34 AD34 AB30 AA30 W30 V30 AB31 AA31 W31 V31 AB33 AA33 W33 V33 AB34 AA34 W34 V34 Signal Category PCI Express (cont.) Table 22 89PES64H16 Alphabetical Signal List (Part 9 of 10) 43 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Signal Name PEREFCLKN0 PEREFCLKN1 PEREFCLKN2 PEREFCLKN3 PEREFCLKP0 PEREFCLKP1 PEREFCLKP2 PEREFCLKP3 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 VDDCORE, VDDAPE, VDDIO, VDDPE, VTTPE VSS I/O Type I I I I I I I I I I I I I I I I/0 I/O I I I I Location V28 G18 U7 AH17 U28 G17 V7 AH18 B32 AH8 AP3 C34 C33 D33 D32 H28 J27 AN4 AP4 AN5 AM5 See Table 20 for a listing of power pins. System System PCI Express System SMBus Interface Signal Category PCI Express (cont.) See Table 21 for a listing of ground pins. Table 22 89PES64H16 Alphabetical Signal List (Part 10 of 10) 44 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet PES64H16 Pinout -- Top View 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP 1 234 5 678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 234 5 678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A B C D E F G X X XX XX X X H J K L M X X X X N P R T XX XX XX XX U V W Y AA X X X X AB AC AD X X XX XX X X AE AF AG AH AJ AK AL AM AN AP VDDCore (Power) VDDI/O (Power) VDDAPE (Power) VDDPE (Power) VTTPE (Power) Vss (Ground) Signals X 45 of 49 No connect July 19, 2007 IDT 89HPES64H16 Data Sheet PES64H16 Package Drawing -- 1156-Pin BL1156/BR1156 46 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet PES64H16 Package Drawing -- Page Two 47 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Revision History July 19, 2007: Initial publication of data sheet. 48 of 49 July 19, 2007 IDT 89HPES64H16 Data Sheet Ordering Information NN Product Family A Operating Voltage AAA Device Family NNAN Product Detail AA Device Revision AA A Legend A = Alpha Character N = Numeric Character Package Temp Range Blank I BL BR ZA Commercial Temperature (0C to +70C Ambient) Industrial Temperature (-40 C to +85 C Ambient) 1156-ball FCBGA 1156-ball FCBGA, RoHS ZA revision 64H16 64-lane, 16-port PES PCI Express Switch H 89 1.0V +/- 0.1V Core Voltage Serial Switching Product Valid Combinations 89HPES64H16ZABL 89HPES64H16ZABR 89HPES64H16ZABLI 89HPES64H16ZABRI 1156-ball FCBGA package, Commercial Temperature 1156-ball RoHS FCBGA package, Commercial Temperature 1156-ball FCBGA package, Industrial Temperature 1156-ball RoHS FCBGA package, Industrial Temperature (R) CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208 49 of 49 July 19, 2007 |
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